1. Field of the Invention
The present invention generally relates to a semiconductor apparatus, and more particularly to a semiconductor apparatus that has a planar capacitor.
2. Description of the Related Art
There is a DRAM (Dynamic Random Access Memory) among fundamental semiconductor apparatuses. In general, the DRAM comprises a single transistor and a single capacitor. In particular, when a DRAM uses a planar capacitor as the capacitor, the structure of the planar DRAM is quite suitable to miniaturization. For this reason, such a planar DRAM is used as a semiconductor memory apparatus. Furthermore, it has been recently attempted to have the planar DRAM serve as a substitute for a high speed memory SRAM (Static Random Access Memory) in a high speed CMOS (Complementary Metal Oxide Semiconductor) logic circuit.
When a DRAM that includes a multi-layer structural capacitor such as a stack capacitor can be implemented in a reduced size, it is impossible to avoid an increase in the thermal budget and degradation of transistor characteristics. For this reason, such a stack capacitor type DRAM has disadvantages in terms of compatibility with a high speed CMOS logic circuit. On the other hand, a planar DRAM can be more easily integrated at a high integration density than a SRAM that includes 6 transistors. Additionally, since the planar DRAM does not use a multi-layer structural capacitor therein, it is possible to reduce the thermal budget. For these reasons, it is considered that the planar DRAM can be suitably used in a high speed CMOS logic circuit.
In a planar capacitor, a cell plate electrode is formed on a substrate via a capacitor insulation film. Here, if a voltage is applied to the cell plate electrode, an inverse layer is induced along a boundary surface between the substrate and the capacitor insulation film. At this time, the induced inverse layer is used as a storage electrode.
In this case, such a planar capacitor has a threshold voltage thereof. In order to drive the planar capacitor, it is necessary to apply a voltage higher than the threshold to the cell plate electrode.
Meanwhile, a current high speed CMOS logic integrated circuit has a CMOS logic element whose gate length is less than 0.18 μm and a gate oxide film whose thickness is less than 3 nm corresponding to the CMOS logic element. The high speed CMOS logic integrated circuit operates at a low voltage of about 1.5 V. On the other hand, the CMOS logic integrated circuit also includes a high voltage transistor driven at a voltage of 3.3 V, for example, an input-output circuit and so on. Therefore, it is preferable that a planar capacitor be formed in the CMOS logic integrated circuit without an increase in the number of fabrication steps, that is, a planar capacitor formed simultaneously with a fabrication process for forming a CMOS logic element and a high voltage element in the CMOS logic integrated circuit.
In a DRAM including a single planar capacitor and a single transfer transistor, it is necessary to satisfy the following condition so as to accumulate electric charge in the planar capacitor;Vcp−(Vb1−Vth1)>Vth2,where Vcp is a voltage applied to an opposite electrode of the planar capacitor, Vb1 is a voltage for writing “1” in the planar capacitor, Vth1 is a threshold voltage of the transfer transistor, and Vth2 is a threshold voltage for forming an inversion layer on a boundary surface between a substrate and a capacitor insulation film of the DRAM. As seen from the condition, as the threshold voltage Vth2 is smaller, the voltage applied to the opposite electrode is allowed to have a wider range. As a result, it is possible to extend the freedom of DRAM design. Conventionally, ions of an impurity element are implanted into a substrate of a semiconductor in order to form a planar capacitor therein. For instance, U.S. Pat. No. 5,986,314 discloses a semiconductor fabrication method through such ion implantation.
A description will now be given, with reference to FIGS. 1A through 1D, of the above-mentioned conventional process for forming a planar DRAM, which comprises a planar capacitor and a transfer transistor, in an integrated circuit simultaneously with a process for providing other MOS (Metal Oxide Semiconductor) transistors in the integrated circuit.
Referring to FIGS. 1A through 1D, a memory cell region 11A and an nMOS (negative Metal Oxide Semiconductor) transistor region 11B are defined on a p-type Si substrate 11 by an element separation structure 12 such as an STI (SHALLOW Trench Isolation) structure. An n-type well 11a is formed in the memory cell region 11A through ion implantation with P (Phosphorus) by using a resist pattern 13A, which covers the nMOS transistor region 11B, as a mask.
Then, As (Arsenic) ions are implanted by using the resist pattern 13A as the mask. As a result, it is possible to form an n-type region 11b, which becomes a channel dope region of the transfer transistor to be formed, in the memory cell region 11A.
In a process in FIG. 1B, a resist pattern 13B is formed so as to cover a transistor formed region in the memory cell region 11A. Then, ions of a p-type impurity element such as B (Boron) are implanted into the memory cell region 11A and the nMOS transistor region 11B by using the resist pattern 13B as the mask. As a result, an n-type impurity region 11c of a low carrier density, which becomes a planar capacitor formed region, is formed in the memory cell region 11A. At the same time, a p-type region 11d, which becomes a channel dope region of the nMOS transistor region to be formed, is formed in the nMOS transistor region 11B.
In a thermal oxidation process in FIG. 1C, thermally oxidized films 14 are formed on the structure in FIG. 1B. In a process in FIG. 1D, a conductive film such as a polysilicon film is deposited on the thermally oxidized film 14. By patterning the conductive film, a gate electrode 15G1 and an electrode 15 are formed on the n-type region 11b in the memory cell region 11A and on the p-type region 11c, respectively. At the same time, a gate electrode 15G2 is formed on the p-type region 11d in the nMOS transistor region 11B. Here, the thermally oxidized films 14 under the gate electrodes 15G1 and 15G2 serve as gate insulation films.
Furthermore, if ions are implanted into the structure in FIG. 1D, which is not illustrated in FIG. 1D, by using the gate electrodes 15G1 and 15G2 as the masks so as to form a source region and a drain region, it is possible to form a transfer transistor in the memory cell region 11A and an nMOS transistor in the nMOS transistor region 11B.
In such a semiconductor apparatus, when a drive voltage is applied to the electrode 15 in FIG. 1D, an inversion layer is induced between the n-type region 11c and the thermally oxidized film 14. As a result, since the inversion layer is used as a storage electrode, it is possible to form a planar capacitor in the memory cell region 11A. Here, the electrode 15 serves as a cell plate electrode, and the p-type diffusion region 11c serves as a storage node. When the planar capacitor constructed in this fashion cooperates with the MOS transistor in the memory cell region, it is possible to provide a planar DRAM.
Meanwhile, as mentioned above, a recent CMOS logic circuit often includes not only a high speed CMOS element driven at a low voltage of about 1.2 V but also a high voltage element driven at a voltage of 3.3 V such as an input-output circuit. In a semiconductor integrated circuit apparatus using a plurality of source voltages in a single substrate, it is necessary to form gate insulation films that have various thicknesses in accordance with the source voltages. Also, it is necessary to use variable doses in a channel dope region in accordance with the source voltages.
Consequently, it is expected to design a semiconductor integrated circuit apparatus fabrication method for forming a semiconductor apparatus having a planar capacitor, typically, a planar DRAM in a semiconductor integrated circuit apparatus using a plurality of source voltages without an increase in the fabrication steps. However, according to the above-mentioned conventional semiconductor integrated circuit apparatus fabrication method, it is impossible to produce such a semiconductor integrated circuit apparatus using a plurality of source voltages without any additional step.
Furthermore, according to the conventional semiconductor integrated circuit apparatus fabrication method, a MOS transistor, which is one part of a DRAM, is formed of an nMOS transistor. However, since the nMOS transistor uses electrons as the carrier, the nMOS transistor is vulnerable to soft errors due to radiation. For this reason, it is desirable to use a pMOS transistor as a memory cell transistor in the DRAM because the pMOS transistor uses holes having larger effective mass as the carrier. In particular, this property of the pMOS transistor is strongly required for a planar DRAM because of a small capacity thereof. However, no semiconductor fabrication method that can overcome the above-mentioned problems has been proposed. Namely, there is currently no semiconductor fabrication method for forming a planar DRAM using a pMOS transistor as a memory cell transistor integrally with a semiconductor integrated circuit apparatus in which a plurality of source voltages are used and a high speed logic circuit is included without any additional processes.